Power line communication for hybrid power/signal pin SOC design

The number of available pins in ball grid array (BGA) of modern system-on-chips (SOCs) has been discussed as one of the major bottlenecks to the performance of the processors, for example many-core enabled portable devices, where the package size and PCB floorplan are tightly constrained. A typical SOC package allocates more than half of the pins for power delivery, resulting in the number of IO pins for off-chip communications is greatly reduced. We observe that the requirement for the number of power and ground (P/G) pins is driven by the highest performance state and the worst design corners, while SOCs are in lower performance state for most of the time for longer battery life. Under this observation, we propose to reuse some of the power pins as dynamic power/signal pins for off-chip data transmissions to increase the off-chip bandwidth during SOC low performance state. Our proposed method provides 20Gbps bandwidth per hybrid pin pair, while providing minimum impact to the original power delivery network (PDN) design.