A New Mapping Methodology for Coarse-Grained Programmable Systolic Architectures

Coarse-grained programmable systolic architectures are designed to meet hard time constraints and provide high-performance computing. They consist of a set of programmable hardware resources with directed interconnections between them. The level of complexity of these architectures limits their re-usability. An automated mapping methodology is required to add a re-usability value to these architectures. In this work, we present a new list-scheduling based mapping methodology for coarse-grained programmable systolic architectures. We use a Directed Acyclic Graph to express the tasks and data dependency of the application as well as the hardware resources organization. We demonstrate that our approach can map different applications, provide a latency estimation and generate the configuration context. This approach could be the base for design space exploration and optimization tools for this family of architectures.