Simulation study of a deep-trench LDMOS with bilateral super-junction drift regions

An improved structure of the Deep-Trench Lateral Double-diffused Metal-Oxide-Semiconductor transistor (DT-LDMOS) is proposed and studied. The most improvement is that a well-known concept of super-junction is simultaneously applied to the bilateral drift regions beside the deep-trench. Thus, in comparison with the conventional device, the Figure of Merit (FOM, which equals BV 2 /R on , sp ) of the proposed one is increased by about 35.6%, which means a significant reduction of conduction loss is achieved. Another improvement is that the device substrate is changed from silicon-on-insulator to ordinary bulk silicon. Therefore, the highest lattice temperature in a heat dissipation test is reduced from about 373 K for the conventional device to about 312 K for the proposed one, which means a better heat dissipation performance is obtained. All in all, the proposed device not only attains a remarkable improvement in electric characteristics, but also possesses an enhanced reliability. It is believed to be a promising device for the monolithic power ICs with enhanced performance.