VLSI Routing Optimization based on modified Constricted PSO with Iterative RLC Delay model

Global interconnect delay is increasingly dominated with the scaling of VLSI fabrication technology where wire minimization, wire-sizing and buffer insertion techniques have found remarkable applications. Multiple researches are proven with state-of-art techniques to solve routing and timing optimization problem in VLSI. Metahueristic being an alternate approach, employed successfully Particle Swarm Optimization (PSO) and Firefly Algorithm (FA) in RC delay Model and Binary PSO (BPSO) for iterative RLC delay model to obtain Global optimum but with limitations. This paper proposes a two-step approach using a modified Constricted PSO with mutation factor where the first stage achieves wire minimization and best buffer insertion with simultaneous wire-sizing in the final stage for reduction of interconnect delay using iterative RLC delay model. A comparison has been made between the conduct of the proposed approach and the previous BPSO approach and is found to be better alternative for optimizing VLSI Interconnect delay.