A study of LDMOS layout optimization of 28HKMG for RF application

LDMOS (Laterally Diffused Metal Oxide Semiconductor) applications get extensively in high voltage and smart power management. In this paper, various LDMOS layout design was studied to get high fT (Cut off frequency) and high breakdown voltage by TCAD simulation based on 28nm HKMG logic process, TCAD simulations reveal that layout and implant optimization can get fT (Cut off frequency) > 50GHz with BV ds (breakdown voltage) > 5V performance on 1.8 V IO NLDMOS.