Effective interconnect networks design in CMOS 45 nm circuits to joint reductions of XT and delay for transmission of very high speed signals

When high speed integrated digital circuits technology scales down from one node to the other as ITRS recommends, a significant gain is obtained on signal speed, consumption and area of CMOS transistors. Nevertheless a specific issue occurs from the 45 nm technology node. The obtained gain on active devices is foiled by an increase of interconnect propagation delays and critical crosstalk (XT) levels in the Back-End of Line (BEOL). This issue especially concerns relatively long (few hundred of μm) interconnects of the intermediate metal level. By introducing drivers (repeaters) in order to divide long interconnect in shorter sections and choosing optimal drivers sizes, speed can be maximized as well as crosstalk levels are alleviated. The present studies aims at specify couple of intervals for both section lengths and drivers size in accordance with speed and crosstalk levels requirements of future ICs. When it becomes hard to meet all requirements, it is shown that the interconnect density constraint should be relaxed.