nML: A Structural Processor Modeling Language for Retargetable Compilation and ASIP Design

Publisher Summary This chapter focuses on the nML architecture description language that models a processor in a concise way for a retargetable processor design and software development tool suite. nML has been carefully designed to contain the right amount of hardware knowledge required by these tools for high-quality results. The tool suite, named IP Designer, offers fast architectural exploration, hardware synthesis, software compilation, instruction-set simulation, and verification. The instruction set is described hierarchically in nML by means of a grammar, with OR rules to specify alternative instruction parts or formats and rules to specify orthogonal instruction parts. nML captures the instructions' behavior in a compact register-transfer model, which exposes the exact resource utilization and pipeline of the processor. This allows for an accurate description of structural and timing irregularities that are typical of many application-specific processors, and is at the basis of patented compilation simulation and hardware generation techniques used in the IP Designer tool suite. nML hazard rules provide efficient solutions for pipeline conflicts, either by stalls or bypasses, and their compact notation gives the designer full control on handling pipeline hazards, playing with the hardware-software trade-off, while being relieved from the detailed hardware implementation of interlocking and feed forward paths.