A biCMOS image signal processor with line memories

An image signal processor which can operate on 512×512 TV images at a 25MHz pixel rate will be described. Two integrated line memories and time division of a parallel processor allow operation, such as 3×3 spatial convolutions, to be executed in realtime using 3 clock cycles. Device has been fabricated in a 1.8μm BiCMOS process with a die area of 104mm 2 .