Characterization of laminated CEO2-HFO2 high-K gate dielectrics deposited by pulsed laser deposition

The electrical and physical properties of CeOa/HfO 2 nanolaminates on silicon are investigated. The layers were deposited by Pulsed Laser Deposition (PLD) on (100) Si after native oxide removal. Layers were deposited using pure CeO 2 and HfO 2 targets at various substrate temperatures ranging from 220 °C to 620 °C. An Ar+H 2 (5 %) backpressure was used to prevent excessive interface oxide formation and to create a reducing environment for Ce 2 O 3 formation. The Ce 2 O 3 is more stable on silicon compared to CeO 2 . In-situ post-deposition anneal (PDA) of nanolaminates was done by controlled cooling from deposition temperature to room temperature under high oxygen pressure (100 mbar). Another approach to control the interfacial oxide re-growth along with the high-k growth was pursued by deposition of a thin Ce layer directly on (100) Si. Approximately 1 nm Ce layer was deposited using an e-beam evaporator. HR-TEM results showed that samples prepared this way resulted in epitaxial layer growth with reduced interfacial oxide growth. After layer growth and anneal, top and bottom Au electrodes were deposited by sputtering. Electrical characterization was done by capacitance-voltage (C-V) and current-voltage (I-V) measurements. The lowest equivalent oxide thickness (EOT) that was found is approximately 2.2 nm, with a leakage current of 2.6.10 -3 A.cm -2 at V fb -1V for 4 nm laminate deposited layer at 420 °C in Ar+H 2 (5%) ambient. The lowest leakage current found is 5.6.10 -6 A.cm -2 for a 12 nm thick layer with an EOT of 3.2 nm, deposited at 520 °C at the same ambient. The interface charge density for the 8 nm thick laminates was found to be 1.3.10 +11 cm -2 with Ce and 4.6.10 +12 cm -2 without Ce layer on Si. In conclusion, it is found that the electrical properties of CeO 2 -HfO 2 nanolaminates deposited at reducing atmosphere are dependent on a layer thickness controlled oxygen diffusion-reaction during post deposition anneal. This results in a higher dielectric constant for increased layer thickness.