Cu Plating of Through-Si Vias for 3D-Stacked Integrated Circuits

In this paper we report on Cu plating of through-Silicon-vias (TSV-s) with a thin Ta film on the field. The thin Ta film is sputtered on top of the Ta barrier/Cu seed, and inhibits Cu plating outside the TSV-s. We show that the use of this Ta-cap and in situ electrochemical monitoring techniques leads to significant savings in plating and polishing time, and thus savings in manufacturing costs of 3D-stacked integrated circuits (3D-SIC).