Compact Model for Double-Gate Tunnel FETs With Gate–Drain Underlap

A compact model for double-gate tunnel FETs (TFETs) with gate–drain underlap (DG u-TFET) is proposed which accounts for the alleviation of ambipolar current and Miller capacitance ( ${C}_{\textrm {dg}}$ ) compared with double-gate tunnel FETs (DG TFET). The ON-state current degradation caused by the underlap is reproduced by extending the ideal DG TFET model with an effective resistance between the channel and the drain. Based on the device surface potential, the terminal charge model is developed which enables the possibility of circuit simulation and the terminal capacitance is further derived from the definition. This model captures the electrical characteristics of DG u-TFET explicitly and good agreement is achieved compared with TCAD simulation. After the model is implemented into HSPICE, an inverter is established and successfully simulated without convergence problem.