IbIS: Interface-based Interconnection Structure for Dynamically Reconfigurable FPGAs

Nowadays SRAM-based FPGAs, already widely used for their advantages in terms of size, flexibility and performances, are becoming even more attractive since they may dynamically change their functionalities based on the elaboration demand, thanks to Dynamic Partial Reconfiguration Feature. In these systems the communication infrastructure represents the major performance bottleneck due to routing congestions and to the needs to guarantee signal integrity at the module boundaries. In this paper we propose an Interface-based communication architecture, which simplify the interaction mechanism and the DRPM architecture, reducing both delay and resources overhead with respect to the state-of-the-art solutions.