An inclusive fault model for Network-on-Chip

In this paper, we propose an inclusive NoC fault model incorporating both high-level abstraction and hardware structure. In high-level abstraction domain, we point out the deficiency of existing fault model as well as simulation procedure, and categorize faults according to their behavior on channel dependency graph CDG. We also introduce connectivity graph CG to identify connection break that faults might incur. In hardware structure domain, we include hardware faults with diverse granularities, and match each hardware fault to corresponding high-level abstraction fault. The fault model we propose shows convincing integrity, and brings more prospects to NoC fault handling.