Reliability design of p/sup +/-pocket implant LDD transistors

It is shown that the reliability design of p/sup +/-pocket LDD (lightly doped drain) transistors is dependent on the pocket implant energy, which controls the positions of the peak field and breakdown regions. A optimum of 60 keV implant in this example gives fairly good ESD (electrostatic discharge) reliability and excellent hot carrier immunity, while preventing transistor punchthrough effects. It is also shown that it is the electric field gradient at the surface rather than the substrate current level that can have a major impact on hot carrier degradation. In fact, for future VLSI transistors this technique can be used to improve the hot carrier reliability. Finally, further insight into the poor ESD performance of LDD transistors is obtained which indicates that the junction breakdown design is important for the ESD performance of LDD or DDD (double diffused drain) transistors. >