Approach to high—speed operation of InGaAs/InP monolithic PIN/Amplifier

We have been developing InGaAs/InP monolithic PIN/Amplifiers. This paper describes the consideration to use self-aligned FETs with a view to improving the operating speed. To this end, the device structure and the fabrication process have first been discussed for integrating the self-aligned JFETs and photodiodes. Next, photodiodes and FETs of this configuration have been fabricated and their characteristics evaluated. It was found that the dark current of the photodiode could be reduced to 2.7 nA at −3 V and that the cutoff frequency of the FET was improved to be 3.0 GHz. Finally, a monolithic PIN/Amplifier was fabricated. Presently, the frequency characteristics of fabricated PIN/Amplifiers are not so good. This is believed to be caused by the fact that the gate electrode of the FET is a Schottky electrode. If this problem is settled in the future, a PIN/Amplifier with a 3-dB bandwidth of about 700 MHz can be realized.