Optimization of the current distribution in press-pack high power IGBT modules

Today's IGBT modules achieve high current ratings by paralleling several semiconductor switches. For high power and high voltage applications, the press-pack IGBT design is a technology of increasing importance, since it is designed for a low inductance series connection in a module stack. This work examines the module-internal current distribution in a press-pack configuration during switching transients by means of the PEEC simulation method. Parasitic effects which result in current unbalances between the paralleled switches are determined and quantified, where special emphasis is put on the power module external interconnection wiring and its influence on the current distribution and power loss in the distinct switches. A hardware test setup is discussed in detail, and a layout design optimization is which balances the loss distribution among the switches.