Modeling and Simulation of Digital Phase-Locked Loop in Simulink

This paper presents a high-level model for a digital phase-locked loop implemented in Simulink. This modeling enables the flexible and fast estimation of the design behavior and parameters before transistor-level implementation. The design includes a digital controlled oscillator that is defined using a linear s-domain model. Furthermore, the design of a time-to-digital converter based on oversampling and noise shaping is introduced to increase the effective resolution of the block. The simulation results of locking process, stability and phase noise verify the functionality of the model.