Decoding circuit and decoding method for FPGA encryption data flow

The invention discloses a decoding circuit of FPGA encryption data flow; the decoding circuit comprises a data input interface, an instruction decoder, a shift register, a secret key memory, a secret key interface module, a secret key expansion module and a decoding module; the data input interface is respectively connected with the instruction decoder and the decoding module; the instruction decoder is connected with the shift register and the secret key interface module; the secret key interface module is connected with the secret key memory and the secret key expansion module; the data input interface is used for inputting encryption data file or secret key instructions, and sending the encryption data file to the decoding module, or sending the secret key instruction to the instruction decoder. The decoding circuit and decoding method for FPGA encryption data flow comprise a specific nonvolatile secret key storage circuit used for storing many secret keys, can carry out multiple encryption and damage encryption; not only the complexity of the decoding circuit is not increased, but also programming speed of the decoding circuit is not reduced, and safety of the encryption data is improved, so decryption and encryption of the FPGA can be more reliable and safe.