Automotive High-Speed Interfaces: Future Challenges for System-level HV-ESD Protection and First- Time-Right Design

This paper describes future design challenges of discrete system-level ESD protection (high-voltage, low-capacitance) of automotive high-speed data links such as multi-gigabit ETHERNET and SERDES/video-links. A special focus is put on an in-depth analysis and accurate modeling of the complex ESD behavior of the Common Mode Choke (CMC). Applied within a System Efficient ESD Design (SEED) simulation concept, this allows a detailed understanding of its multifaceted interaction with modern vs. standard ESD discrete components. As demonstrated for advanced data-link ESD protection requirements, this approach can provide important system optimization steps thus enabling first-time-right ESD-RF co-design.