An architecture of highly parallel computer AP 1000

A highly parallel computer with distributed memory called the AP1000 has been developed. The system consists of 64 and 1024 processing elements and three independent networks called the torus network (T-net), broadcast network (B-net), and synchronization network (S-net). The design goal for the AP1000 is to attain low-latency, high-throughput communication. To reduce the overall communication latency, a message controller and a new routing scheme on the T-net have been developed. The design concepts, architecture, and some results from performance tests for the AP1000 are presented. >