Considerations in High Voltage Lateral ESD PNP Design

This work investigates design options for three different classes of high voltage lateral ESD PNPs in a 0.5-µm BCD technology. The PNP layout topology is observed to affect the area efficiency as well as the device's I-V characteristic. Collector-tied field plates exert significant control over the device's turn-on voltage, and this is explored using TCAD. A “two-valued on-resistance” is observed in some PNP devices, depending on the doping profile.