Modeling of STI-induced stress phenomena in CMOS 90nm Flash technology

A non negligible layout sensitivity of MOSFETS electrical behavior has been recently observed in advanced CMOS technologies. Some efforts have been attempted to encapsulate this phenomenon in Spice-like simulation oriented models. In the present work, we suggest improvements to previously proposed approaches, after a critical discussion about them. An extensive characterization of CMOS 90 nm Flash memory technology is the support of our issues. Finally, simulation of prototype circuits shed some light on the impact of STI stress in IC design.