Measurement of inner-chip variation and signal integrity by a 90-nm large-scale TEG [test element group]

We have developed the world's first measurement methodology for both inner chip variation and SI (signal integrity) in the same 90 nm large scale TEG (test element group = test structure). And we have successfully measured the yield of inner chip variation and also the yield of SI by a logic tester. Those two characteristics in a chip or in a wafer were evaluated in a detailed analysis, directly. The contribution to this new technology's success comes from two features of the test structure. One is an address decoder circuit, another is the large length wire configurations or large number of devices. Evaluated data showed new helpful information about the relationship between inner chip variation and SI including the phase difference effect, thus leading to a robust physical design, considering process variation and signal operation conditions. This new technology will make an impact and produce a new stage of both SoC circuit design and deep submicron process technology.