Characterization of Single-Event Upsets Induced by High LET Heavy Ions in 16 nm bulk FinFET SRAMs

For advanced technology nodes, the static random-access memories (SRAMs) are highly vulnerable to the single-event upsets (SEUs), especially the multiple cell upsets (MCUs), by a high energy ion strike, which is due to the small transistor size and close proximity of the sensitive regions. However, the narrow connection between the fin and the bulk region for FinFET inhibits the charge collection compared to the planar transistor structure. In this work, heavy ion tests were conducted for 16 nm bulk FinFET dual-port SRAM at two high linear energy transfers (LETs) of 60 MeV∙cm2/mg and 85 MeV∙cm2/mg. The non-saturating behavior of the SEU cross-sections and event cross-sections for a bit cell is observed even over the LET of 60 MeV∙cm2/mg due to the expanding of the sensitive area surrounding the array and the cutting-off area in the FinFET SRAM cells. The distribution curves of the MCU event probabilities for different MCU cluster sizes show the Single-bit upset (SBU) occupies the largest probability of all the single-event cluster sizes, which exhibits the inhibition capability of the Fin structure against the upsets induced by high energy particles. The parasitic bipolar effect is also serious for 16nm FinFET SRAM as former planar SRAM, but the charge sharing effect is effectively inhibited due to the narrow connection between the fin and the bulk region for FinFET. Results presented in this paper will help designers estimate the Error Correcting Code (ECC) and interleaving design parameters for radiation hardened SRAM designs at the 16 nm FinFET process.