A 10-bit 400-MS/s 36-mW interleaved ADC

A high-speed interleaved pipelined ADC employs a global track-and-hold (T/H) circuit in front of the ADC to avoid sampling time mismatches between channels. Each sub-channel ADC employs both opamp-and time-sharing techniques to reduce power consumption and silicon area. The proposed ADC has been fabricated in a 90-nm digital CMOS technology and occupies 0.38 mm 2 . It operates at 400 MS/s and achieves an SNDR of 53.0 dB while the power consumption is 36 mW including an on-chip reference buffer.