Mismatch Reduction Techniques for Current-Mirror Based Potentiostats

Current-mirror based potentiostats suffer from systematic and random errors that mainly appear due to mismatch in the current-mirror. To limit the standard deviation of the error to less than 1.1 % over a dynamic range of four decades, either a high overdrive voltage or comparable big transistor dimensions are required. In this work, an optimized design approach for the current-mirror is presented. Based on the given accuracy and dynamic range requirements, an optimized programmable current-mirror is implemented. An accuracy driven design approach is used to achieve the required accuracy over the wide range of sensor currents, while keeping the area consumption low. Compared to a linearly scaled current-mirror based potentiostat design, an output stage area reduction by a factor of four is achieved. Additionally, the voltage headroom consumption is kept at a minimum. The potentiostat is implemented in a 130 nm CMOS technology and consumes an area of only 0.14 mm2. The simulation results show that even in the worst case the specified accuracy is achieved over the complete dynamic range of sensor currents from nA to mA.