Clock frequency 2-multiplier

PURPOSE: To provide a circuit which generates a non-superposed complementary clock signal having a double frequency from an input signal and settles a prescribed phase relation between a single frequency signal and the double frequency signal and can be integrated. CONSTITUTION: A NAND flip flop 2 has complementary outputs to obtain a clock signal of the double frequency. One of outputs of the NAND flip flop 2 is inputted to a clock input H of a D flip flop 3, and its output QD is connected to its data input D through an inverter. The input clock signal and its complementary signal are inputted to first inputs of two exclusive OR gates X01 and X02 respectively, and the output of the D flip flop is inputted to second inputs. Outputs of exclusive OR gates are connected to inputs E1 and E2 of the NAND flip flop respectively. COPYRIGHT: (C)1992,JPO