Measurement of Inner-chip Variation and Signal Integrity By a 90-nm Large-scale TEG

We have developed the world first measurement methodology of both inner chip variation and SI(signal integrity) in a same 90nm large scale TEG (Test Element Group = test structure). And we have successfully measured the yield of inner chip variation and also the yield of SI by the logic tester. Those two of the characteristics in a chip or in a wafer were evaluated in detail analysis directly. Contribution to this new technology’ success comes from the two features of the test stmcture. One is address decoder circuit, another is large length wire’s configurations or large number of devices. Evaluated data showed new helpful information about the relationship between inner chip variation and SI including phase difference effect, those ate leading to the robust physical design considering process variation and signal operation condition. This new technology will make impact and give a new stage of both SoC circuit design and deep submicron process technology.