Temperature efficient parallel test scheduling for higher order 3D stacked SoCs

Test Scheduling is an important area of research in VLSI Testing. Nowadays, efficient testing is an area of concern in electronics industry. Testing of VLSI circuit mandates fast, cost effective testing which is complete in itself and yields results nearing perfection. In VLSI testing, huge temperature is created and therefore temperature management is an important factor. For addressing temperature issues, effective test scheduling is resorted to and is found to be effective. Undoubtedly, testing is a tedious and time consuming task. Authors have worked on scheduling for 3D SoC testing earlier and in this paper, the same is implemented on higher order and intricate circuitry where focus lies on keeping a check on temperature rise and testing time. As heat gets trapped in layers, 3D SoCs, testing accumulates much more heat than planar circuits. Here an attempt is made to manage temperature rise during testing of 3D SoCs by effective scheduling the test sets. Novel scheduling, as earlier used by authors is implemented on 3D SoCs and results are quite encouraging. The algorithm is designed in such a way that temperature rise of each core is monitored during testing. It is compared with standard work. The simulation is done on HotSpot-6.02 using standard benchmark circuits. Along with managing the time of testing, a strict vigil is on heat generation is inescapable as temperature rise results in formation of Hotspots which lead to damage to circuits. Test scheduling is undoubtedly a large area of research. In this paper the algorithm based on adjacency exclusion principle for test set scheduling is employed which aims to keep the temperature under check and also limiting the time required.