Double Hysteresis Loops in Proper Uniaxial Ferroelectrics

Identifying high-performance materials for ferroelectric-memory technology ($e.g.$ FeRAM) is important for increasing the density of information storage. Here the bulk room-temperature ferroelectric semiconductor Sn${}_{2}$P${}_{2}$S${}_{6}$ is studied, and the results demonstrate the possibility of its use as an active material in a multilevel ferroelectric memory cell. In addition, a model is presented to explain the coexistence of ferroelectric and antiferroelectric hysteresis loops in Sn${}_{2}$P${}_{2}$S${}_{6}$.