Design and Comparison of Synthesizable Fair Asynchronous Arbiter

Asynchronous Arbiters are an important component of asynchronous circuits. Several versions of asynchronous arbiters designed with Mutual exclusion elements and/or Muller C-elements have been proposed so far. They vary in the number of transistors used, responsiveness to client requests and the ability to be synthesized through Hardware Description Language (HDL). In applications such as Network-on-Chip, which use a large number of arbiters, the number of transistors used and HDL synthesizability are critical. This paper presents an improved 2-way asynchronous arbiter circuit for such applications. It also presents a comprehensive review and comparison of previously proposed solutions. All the compared arbiters were simulated in TSMC 65nm CMOS technology.