A VLSI processor for concurrent list intersection

The functionality, architecture and design of a VLSI array processor for list intersection is presented. A NMOS implementation on a 5×5 mm2 chip, with lambda rules using a 2.5 μm line witdth process is considered. The resulting chip, totaling 55,000 transistors, is organized in 16 comparison and 15 supply cells operating cuncurrently. Limits and potentialities of the processor are discussed.