DISEÑO DIGITAL CON FPGAS Y MICROPROCESADORES Digital desig with fpgas and microprocessors

This article describes the design and implementation of a system that displays some sequences and messages on a FPGA. The paper shows the development of logic implemented in VHDL code for a down counter of four (4) digits in 9999-0000, showing an upward counting stopwatch minutes and seconds (mm: ss) 00:00 59 59, a message of four letters and a message of at least 10 characters which are displayed dynamically in the four (4) of the seven-segment displays NEXYS2 card.