High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique

High performance CMOSFET technology for 45nm generation is demonstrated. The key device strategies for junction scaling, gate stack scaling and stress-induced mobility enhancement are discussed. Reversed-order junction formation improves short channel effect (SCE) drastically. Novel SiON with improved poly-Si gate depletion improves the drive current by 8%. The systematic study on the process-induced mobility enhancement is performed and it is confirmed that the new scheme such as eSiGe and stress liner techniques are suitable for 45nm technology CMOSFET. It is confirmed that the stress enhancement factors using multiple booster techniques remain valid, which proves that these techniques are scalable for future technology