AMBA APB Memory Controller Functional Verification using SystemVerilog

In this paper we present, the design and perform verification of APB (Advanced Peripheral Bus) memory block. A SystemVerilog code is developed for an AMBA APB based memory block, for modelling memory and the read and write operation is verified. For verification we have used SystemVerilog which is a hardware description and verification language. It is an extension of the very popular language Verilog. The most important advantages of using this language are its ability of random constrained-based verification and reusability. Random constraint-based verification can be effectively used for verifying large complex designs as it can automatically generate a large number of random test cases and can hit corner cases faster. Verification engineers may not always write a verification environment from scratch, they can also modify an existing one. These features are readily available in SystemVerilog. Cadence is a software system for integrated circuit design and verification and it is used to simulate and verify our design and calculate the functional coverage. The functional coverage obtained was 100% when each coverpoint had two bins (for low and high values).