Design of radiation hard CMOS APS image sensors in a 0.35-μm standard process

A CMOS APS Image sensor test chip was designed employing the physical design techniques of enclosed geometry and guard ring, and according to the design rules of a 0.35-micrometers CMOS standard process that has a gate oxide thickness of approximately 7.0 nm. Three sets of radiation tolerant photodiode active pixels were developed employing these design techniques. They are N-type, and H-type pixels. Each of the pixels is a square pixel with a 16.2 micrometers pitch. The yielded fill-factor is approximately 50 percent. Depending on the pixel-type and the layout, the simulated output voltage swing ranges from 300 mV to 1.1 V. The peripheral circuits, which include decoders, row/column drivers, and I/O pads, were also developed. All NMOS transistors in the peripheral circuits were laid out employing the physical design techniques of enclosed geometry and P-type guard ring. Integrating the pixels and the peripheral circuits into the design of radiation hard CMOS APS image sensor has bene completed. The size of the pixel array is 256 by 256, constituting an imaging area of approximately 4.1 mm X 4.1 mm. The total size of the die is approximately 5.2 mm X 5.0 mm. The total number of the I/O pads is 42. Plans to irradiate these image sensor using Cobalt-60 to determine the level of their radiation hardness are currently being devised.