Highly manufacturable 100 nm 6T low power SRAM with single poly-Si gate technology

As scaling down the device, it is difficult to control the standby leakage and device performance at the same time. In this work, 6-transistor SRAM cell using buried channel PMOS technology was introduced and the device for low power consumption was analyzed. The major source of leakage current on NMOS and PMOS devices was different pathways, and it was controlled by reduction of gate poly-Si oxidation thickness and the optimization of LDD implantation process. The load PMOS lifetime under the HEIP stress was over 10 years at 3.5V of operation voltage. The SNM margin was obtained in subthreshold operation region by increase the current of load transistor and compensated for the process variation. Finally, SRAM cell of 0.84 /spl mu/m/sup 2/ of size with 0.1 /spl mu/m design rule was successfully fabricated.