Mixed increasing filter pipeline design for H.264/AVC deblocking filter

A mixed increasing filter pipeline and its on-chip memory architecture were proposed in order to address the challenges of main-profile deblocking filter.The filter adopts mixed increasing filtering order for main-profile deblocking filter and uses six-stage pipeline for parallel filtering on target pixels.The memory architecture can efficiently support both row/column and frame/field data access in main-profile filter.Then pipeline stall and off-chip DRAM access were reduced by improving the granularity of data reusability.Experimental results show that the architecture can achieve better tradeoff between hardware cost and performance improvement compared with the related works.At the hardware cost of 25.7K gate cell and 768 Byte SRAM,three parallel real time deblocking filter for 1080P HDTV H.264 main-profile video stream can be realized.