Automated design space exploration of transient fault detectable datapath based on user specified power and delay constraints

A novel automated design space exploration (DSE) approach of multi-cycle transient fault detectable datapath based on multi-objective user constraints (power and delay) during high level synthesis (HLS) is presented in this paper. To the best of the authors' knowledge, this is the first work in the literature to solve this problem. The presented approach, driven by bacterial foraging optimization (BFO) algorithm provides easy flexibility to change direction in the design space through tumble/swim actions if a search path is found ineffective. The approach is highly capable of reaching true Pareto optimal region indicated by the closeness of our non-dominated solutions to the true Pareto front and their uniform spreading over the Pareto curve (implying diversity). The contributions of this paper are as follows: a) novel exploration approach for generating high quality transient fault detectable structure based on user provided requirements of power-delay, which is capable of transient error detection; b) novel fault detectable algorithm for handling single and multi-cycle transient faults. The results of the proposed approach indicated an average improvement in Quality of Results (QoR) of >9% and reduction in hardware usage of > 26 % compared to recent approaches that are closer in solving a similar objective.