A 10mW 9.7ENOB 80MSPS pipeline ADC in 65nm CMOS process without any special mask requirement and with single 1.3V supply

This paper describes a power and area efficient pipeline ADC design. This ADC was designed in 65nm process without any special mask requirement and can work with supply voltage of 1.3V consuming 10mW providing 9.7 ENOB at 80MSPS while occupying less than 0.2 square millimeters.