Reconfigurable Adaptive Routing Buffer Design for Scalable Power Efficient Network On Chip

The layout density of integrated circuits on a single chip has led to the reduced size at sub-micron scales of VLSI design. The System on Chip (SOC) design has few challenges, such as latency, power, area and reliable data transmission among sub-systems interconnected on a single chip. Network on Chip (NOC) is a subset of SOC which accomplishes on-chip communication process. The performance of NOC architecture is significantly affected by power and area. This research work has focused on a new low power reconfigurable NOC architecture with repeaters between the routers. The repeater enables zero buffers between the interlink routers. It works on the principles of store and forward process. The proposed architecture is implemented using mesh network topology. The simulated results of new architecture have shown a reduction in power dissipation by 56% and reduction in on chip area by as much as 60%.