Towards Massively-Parallel Analytic Capabilities for Multielectrode Recordings

Multielectrode recordings now reliably deliver simultaneous signals from a hundred or more neurons or networks. However, many analytic techniques are presently computationally limited to smaller numbers of signals, severely limiting our ability to relate these neural signals to brain functions including sensation, perception, decision, and action.To address this imbalance, we are developing a new open source Neurophysiology Extended Analysis Tool. NEAT leverages existing code bases and new massively-parallel computational technology to enable any multielectrode lab to perform high-throughput informative analyses. We begin with linked evaluations of: 1) computational bottlenecks in analytic routines, many information-theoretic, developed for our Spike Train Analysis Toolkit and distributed via neuroanalysis.org to over 1,600 sites [Goldberg et al. Neuroinformatics 7, 165-178, 2009], and 2) specific capabilities and restrictions of new graphics-processor-derived computational engines supplied on inexpensive drop-in cards.We project a greater than order of magnitude speedup that will allow many offline analyses to be performed in real time during experiments, and now-impractical questions to be explored offline in reasonable compute times. For example, pairwise analyses now possible on 10 or fewer neurons may be extendible to 50 or more. We focus on information-theoretic measures and standard pair-wise correlations, JPSTHs, spectra, coherences, and new and significant analyses that present significant loads for multineuron recordings.To aid communities planning similar GPU-enabled analyses, we note that the complex, structured, and hierarchic GPU architecture requires special optimization strategies:• decomposing code into >1,000 simultaneous threads is needed to efficiently use the 448 cores on new GPUs,• data should be loaded into on-chip memory once and re-used, avoiding transfers to other memory layers,• kernel processes must optimize thread/kernel and thread/block instruction execution in few clock cycles,• flow control code should control multi-thread warps, not individual threads.Support: MH057153/MH068012.