A high performance 90 nm logic technology with a 37 nm gate length, dual plasma nitrided gate dielectric and differential offset spacer

A 90 nm logic technology is presented featuring an aggressively scaled 37 nm gate length, 1.3 nm EOT plasma nitrided gate dielectric with differential offset spacer and leading edge CV/I performance. NMOS and PMOS transistors have been optimized with different extension offsets for NMDD and PMDD implants, which enables independent optimization of short channel effects, parasitic capacitance and drive current. The gate dielectric meets reliability requirements at 1.2 V operation. The technology includes a standard Vt (SVt) transistor, low Vt (LVt) transistor and 1.5 V IO transistor with l00 nm gate length and dual plasma nitrided gate dielectric.