Defectivity Study of PMOS S/D implants on a Spot Beam High Current Implanter

As DRAM devices scale below the 30 nm node, the device performance requirements for the input/output CMOS circuits are increasing significantly. Specifically, short channel effects (SCE) and their associated leakage currents are becoming increasingly problematic. Various forms of implant damage engineering are being investigated to minimize leakage from SCE. These include changes to the implanter architecture (spot vs. ribbon beam), implantation temperature, and implant species (monomer vs. molecular). We studied the defect morphology both after ion implantation and after annealing for the PMOS S/D implant on an advanced DRAM device. The implants were combinations of BF2, (B18H22)2, C, and C16H10. Implant temperatures ranged from −30 °C to +20 °C. Thermawave, SIMS, Rs and TEM were used to characterize the samples.