Effects of Threshold Voltage Variations on Single-Event Upset Response of Sequential Circuits at Advanced Technology Nodes

Threshold voltage ( ${V}_{T}$ ) of transistors plays an important role in single-event upsets (SEU) and system power consumption. Effect of $\text{V}_{\text {T}}$ on single-event upsets can be very different for different technologies. SEU responses of flip-flops and logic circuits in 20-nm bulk planar and 16-nm bulk FinFET technologies with different $\text{V}_{\text {T}}$ options are investigated. Results show that for the 20-nm bulk planar technology, the design with the highest threshold voltage among all $\text{V}_{\text {T}}$ options shows the lowest SEU cross-section for alpha particle irradiation. For the 16-nm FinFET technology, the option with the highest threshold voltage shows the highest SEU cross-section. As frequency increases, the SEU cross-section of the highest $\text{V}_{\text {T}}$ design shows a faster increase and a larger curve slope due to increased single-event transient (SET) pulse width compared to the lower $\text{V}_{\text {T}}$ designs for the 16-nm FinFET technology node.