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Design of 32-bit cell-based carry-save combinational multiplier with reduced area and propagation delay
Design of 32-bit cell-based carry-save combinational multiplier with reduced area and propagation delay
2021
Shruti Suman
Ngangbam Phalguni Singh
R. Selvakumar
Harshita Saini
Keywords:
Propagation delay
cell based
32-bit
Electronic engineering
Multiplier (economics)
Computer science
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