An 8-bit 2.8 GS/s Flash ADC with Time-based Offset Calibration and Interpolation in 65 nm CMOS

An 8-bit 2.8 GS/s flash ADC with time-based offset calibration and interpolation is realized in 65 nm CMOS. The proposed time-based offset calibration uses intentional timing skew for offset cancellation without adding extra load to comparators, thus avoiding the speed penalty. The time-based 4x interpolation reduces the number of comparators to 1/4 and provides calibration capability for 8-bit accuracy through SR latches and delay lines. At 2.8 GS/s, the prototype consumes 51 mW from a 1-V supply and achieves Nyquist SNDR of 43.3 dB, effective resolution bandwidth (ERBW) of 1.52 GHz, and Walden figure-of-merit (FoM) of 153 fJ/conv-step, reporting a higher Nyquist ENOB than state-of-the-art single-channel flash ADCs with comparable FoM.