Comparative study of InP/InGaAs double heterojunction bipolar transistors with InGaAsP spacer at base-collector junction

In this article, the influence of InGaAsP spacers inserted at base-collector (B-C) junction in the InP/In0.53Ga0.47As double heterojunction bipolar transistors is demonstrated by two-dimensional semiconductor simulation. Due to the addition of an InGaAsP spacer layer, two small potential spikes are formed at B-C junction and the current blocking effect is reduced. The results exhibit that the maximum current gain increases from 30 to 374 (375) as the thickness of InGaAsP spacer layer varies from 0 to 100 A (300 A). On the other hand, the device with a thicker spacer layer (300 A) could effectively improve the knee effect of the current-voltage curves as compared the other devices. In addition, the collector-emitter offset voltages less than 10 mV are observed in the three devices.