Resilient Dataflow Graph Embedding for Programmable Software Switches

Programmable software switches have become crucial building blocks in a wide range of applications, from (virtual) data center networking to telco clouds. Modern use-cases, such as 5G, require very low latency, large throughput, and high availability. Software switches generally realize the packet processing pipeline as a dataflow graph: graph nodes correspond to simple packet processing operations and graph edges represent the control flow. The efficiency and dependability of the software switch critically depends on the way the dataflow graph is mapped to the underlying hardware resources. In this paper, we focus on dataflow graph embedding in a software switching context. We present an embedding approach which minimizes performance loss on inter-CPU communication across packet-processing control flow chains, and is resilient against a single CPU failure. The embedding is easy to generalize to $N$ CPU failures. We formulate the dataflow graph embedding problem as a mathematical program, characterize the computational complexity, and we propose optimal and heuristic algorithms to solve it. The viability of our approach is confirmed in comprehensive numerical analysis on a 5G packet processing pipeline, taken from an industrial 5G NFV benchmark suite.