Enhancement mode GaN transistor device

The invention discloses an enhanced gallium nitride transistor device. The enhanced gallium nitride transistor device comprises a substrate, an epitaxial structure on the substrate, a concave grid on the epitaxial structure, a grid electrode on the concave grid, a source electrode and a drain electrode. The concave grid is a p-type metallic oxide. A dielectric lamination is arranged between the grid electrode and the concave grid. The dielectric lamination comprises a first dielectric layer and a second dielectric layer, wherein the second dielectric layer is in touch with the concave grid, and the oxidation potential of the metallic element in the second dielectric layer needs to be lower than that of the metallic element of the p-type metallic oxide. The concave grid has a nano-structure pattern, and the nano-structure graphic is extended into the epitaxial structure.